With continuous scaling down of semiconductor devices, short channel effects are becoming more significant. Thus, a gate stack configuration comprising a high-K gate dielectric and a metal gate conductor is proposed. To avoid degradation of the gate stack, semiconductor devices with such a gate stack configuration are manufactured generally by means of the replacement gate process. The replacement gate process involves filling the high-K dielectric and the metal gate conductor in a gap defined between gate spacers. However, it is becoming more and more difficult to fill the high-K dielectric and the metal gate conductor in the small gap due to the scaling down of the semiconductor devices.
On the other hand, semiconductor devices formed on Extremely Thin Semiconductor On Insulator (ET-SOI) substrates have good control of the short channel effects and relatively small random fluctuation of dopants. However, the ET-SOI substrates are expensive in cost.